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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
BIGIP i5820 OpenSSL Implementation
Description
F5® BIG-IP® Application Delivery Controller and Firewall software running on F5 BIG-IP.
Version
13.1.0 (Firmware)
Type
SOFTWARE
Vendor
F5 Networks
401 Elliott Avenue West
Seattle, WA 98119
USA
Contacts
Maryrita Steinhour
m.steinhour@f5.com
206-272-7351
John Hughes
j.hughes@f5.com
206-272-6038

ECDSA 1219

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 ECDSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA KeyVer (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA SigVer (FIPS186-4) Expand

Component 1445

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 KDF SSH Expand
Intel(R) Xeon(R) CPU E5-1630 KDF TLS Expand

Component 1444

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 KAS-ECC CDH-Component Expand
Intel(R) Xeon(R) CPU E5-1630 KAS-ECC Component Expand

DRBG 1681

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 Counter DRBG Expand

RSA 2642

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 RSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 RSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 RSA SigVer (FIPS186-4) Expand

HMAC 3223

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA-1 Expand
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA2-256 Expand
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA2-384 Expand

AES 4822

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 AES-CBC Expand
Intel(R) Xeon(R) CPU E5-1630 AES-ECB Expand
Intel(R) Xeon(R) CPU E5-1630 AES-GCM Expand
Intel(R) Xeon(R) CPU E5-1630 AES-GMAC Expand

SHS 3964

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 SHA-1 Expand
Intel(R) Xeon(R) CPU E5-1630 SHA2-256 Expand
Intel(R) Xeon(R) CPU E5-1630 SHA2-384 Expand

Created October 05, 2016, Updated March 07, 2023