U.S. flag   An unofficial archive of your favorite United States government website
Dot gov

Official websites do not use .rip
We are an unofficial archive, replace .rip by .gov in the URL to access the official website. Access our document index here.

Https

We are building a provable archive!
A lock (Dot gov) or https:// don't prove our archive is authentic, only that you securely accessed it. Note that we are working to fix that :)

Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
BIGIP i4000 OpenSSL Implementation
Description
F5® BIG-IP® Application Delivery Controller and Firewall software running on F5 BIG-IP.
Version
13.1.0 (Firmware)
Type
SOFTWARE
Vendor
F5 Networks
401 Elliott Avenue West
Seattle, WA 98119
USA
Contacts
Maryrita Steinhour
m.steinhour@f5.com
206-272-7351
John Hughes
j.hughes@f5.com
206-272-6038

Component 1449

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 KDF SSH Expand
Intel(R) Xeon(R) CPU E5-1630 KDF TLS Expand

AES 4824

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 AES-CBC Expand
Intel(R) Xeon(R) CPU E5-1630 AES-ECB Expand
Intel(R) Xeon(R) CPU E5-1630 AES-GCM Expand
Intel(R) Xeon(R) CPU E5-1630 AES-GMAC Expand

RSA 2644

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 RSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 RSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 RSA SigVer (FIPS186-4) Expand

HMAC 3225

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA-1 Expand
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA2-256 Expand
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA2-384 Expand

Component 1448

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 KAS-ECC CDH-Component Expand
Intel(R) Xeon(R) CPU E5-1630 KAS-ECC Component Expand

DRBG 1683

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 Counter DRBG Expand

ECDSA 1221

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 ECDSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA KeyVer (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA SigVer (FIPS186-4) Expand

SHS 3966

   First Validated: 10/27/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 SHA-1 Expand
Intel(R) Xeon(R) CPU E5-1630 SHA2-256 Expand
Intel(R) Xeon(R) CPU E5-1630 SHA2-384 Expand

Created October 05, 2016, Updated March 07, 2023