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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Sypher AES-256-bit Encryption FPGA Module
Description
Firmware (FPGA) implementation providing AES support to encrypt/decrypt radio traffic communication.
Version
1.00
Type
HARDWARE
Vendor
Analog Devices Inc.
13008 Telecom Drive
Suite 100
Tampa, FL 33637
USA
Contacts
Barry Dowdy
barry.dowdy@analog.com
813-559-6612
Fax: 813-221-1124
Nicole Nicholson
nicole.nicholson@analog.com
813-559-6650
Fax: 813-221-1124

AES 5177

   First Validated: 1/26/2018
Operating Environment Algorithm Capabilities
Sypher AES-256-bit Encryption FPGA Module AES-CTR Expand
Sypher AES-256-bit Encryption FPGA Module AES-ECB Expand

Created October 05, 2016, Updated March 07, 2023