A depth-16 circuit for the AES S-box

Boyar, Joan; Peralta, Rene

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A depth-16 circuit for the AES S-box

Documentation Topics

Date Published: 6/17/2011

Author(s)

Joan Boyar (University of Southern Denmark), Rene Peralta (NIST)

Abstract

New techniques for reducing the depth of circuits for cryptographic applications are described and applied to the AES S-box. These techniques also keep the number of gates quite small. The result, when applied to the AES S-box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-box and its inverse, consisting of 63 gates.

Keywords

AES; S-box; finite field inversion; circuit complexity; circuit depth

Control Families

None selected

Documentation

Publication:
Paper

Supplemental Material:
None available

Document History:
06/17/11: Other (Final)

Topics

Security and Privacy

encryption

Technologies

circuits, complexity