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Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
BigIP B4000 TMM Implementation
Description
F5® BIG-IP® Application Delivery Controller and Firewall firmware running on F5 BIG-IP.
Version
13.1.0 (Firmware)
Type
SOFTWARE
Vendor
F5 Networks
401 Elliott Avenue West
Seattle, WA 98119
USA
Contacts
Maryrita Steinhour
m.steinhour@f5.com
206-272-7351
John Hughes
j.hughes@f5.com
206-272-6038

Component 1470

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU KDF TLS Expand

HMAC 3235

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU HMAC-SHA-1 Expand
Intel(R) Xeon(R) CPU HMAC-SHA2-256 Expand
Intel(R) Xeon(R) CPU HMAC-SHA2-384 Expand

AES 4834

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU AES-CBC Expand
Intel(R) Xeon(R) CPU AES-GCM Expand
Intel(R) Xeon(R) CPU AES-GMAC Expand

ECDSA 1231

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU ECDSA KeyGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU ECDSA KeyVer (FIPS186-4) Expand
Intel(R) Xeon(R) CPU ECDSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU ECDSA SigVer (FIPS186-4) Expand

Component 1469

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU KAS-ECC CDH-Component Expand
Intel(R) Xeon(R) CPU KAS-ECC Component Expand

RSA 2654

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU RSA SigGen (FIPS186-4) Expand
Intel(R) Xeon(R) CPU RSA SigVer (FIPS186-4) Expand

DRBG 1693

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU Counter DRBG Expand

SHS 3976

   First Validated: 11/3/2017
Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU SHA-1 Expand
Intel(R) Xeon(R) CPU SHA2-256 Expand
Intel(R) Xeon(R) CPU SHA2-384 Expand

Created October 05, 2016, Updated March 07, 2023