Computer Security Resource Center

Computer Security Resource Center

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    Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Cryptographic library for TOP DL V2.1
Description
TOP DL V2.1 is a highly secured smartcard platform compliant with the Javacard 2.2.2, GP 2.1.1 & GP 2.2 Amdt D standards, designed to operate with the NXP P60xx chip. It supports: TDES, AES, AES-CMAC, SHA1-224-256-384-512, RSA, RSA CRT, ECDSA, ECC CDH, KDF SP800-108 & DRBG SP800-90A algorithms.
Version
NXP P60 FM Version 2.1 (Firmware)
Type
FIRMWARE
Vendor
Gemalto
Avenue du Jujubier
Z.I Athelia IV
La Ciotat, 13705
France
Contacts
Frederic GARNIER
Frederic.Garnier@gemalto.com
+33 442364368
Fax: +33 442366953
Carlos Romero-liceras
Carlos.Romero-liceras@ gemalto.com
+33 442365666
Fax: +33 442365545

RSA 1822 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family RSA KeyGen (FIPS186-4) Expand
NXP SmartMX2 P60 chip family RSA SigGen (FIPS186-4) Expand
NXP SmartMX2 P60 chip family RSA SigVer (FIPS186-2) Expand
NXP SmartMX2 P60 chip family RSA SigVer (FIPS186-4) Expand

ECDSA 721 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family ECDSA KeyGen (FIPS186-4) Expand
NXP SmartMX2 P60 chip family ECDSA SigGen (FIPS186-4) Expand
NXP SmartMX2 P60 chip family ECDSA SigVer (FIPS186-4) Expand

SHS 2921 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family SHA-1 Expand
NXP SmartMX2 P60 chip family SHA2-224 Expand
NXP SmartMX2 P60 chip family SHA2-256 Expand
NXP SmartMX2 P60 chip family SHA2-384 Expand
NXP SmartMX2 P60 chip family SHA2-512 Expand

TDES 1984 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family TDES-CBC Expand
NXP SmartMX2 P60 chip family TDES-ECB Expand

AES 3543 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family AES-CBC Expand
NXP SmartMX2 P60 chip family AES-CMAC Expand
NXP SmartMX2 P60 chip family AES-ECB Expand

DRBG 900 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family Counter DRBG Expand

Component 597 Expand All First Validated: 10/16/2015

Operating Environment Algorithm Capabilities
NXP SmartMX2 P60 chip family KAS-ECC CDH-Component Expand

Created October 05, 2016, Updated December 18, 2020