Computer Security Resource Center

Computer Security Resource Center

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    Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
Nitrox III series die
Description
NITROX III chips implement SHA1/SHA2, 3DES/AES256 CBC, ModMul/ModEx/RSA, GCM and CTR modes, and SP800-90A DRBG. Perf: 5 to 30 Gbps encrypt/hash; 35K to 200K RSA 1024b ops/sec; 6K to 35K RSA 2048b ops/sec. NITROX III microcode also implements protocol-specific acceleration for IPSec and SSL.
Version
Nitrox III Series Die, v1.1
Type
HARDWARE
Vendor
Cavium, Inc.
2315 N. First Street
San Jose, CA 95131
USA
Contacts
Mike Scruggs
mike.scruggs@cavium.com
(408) 943-7100
Fax: (408) 577-1992
TA (TAR) Ramanujam
tar@cavium.com
(408) 943-7383
Fax: (408) 577-1992

HMAC 1233 Expand All First Validated: 5/25/2012

Operating Environment Algorithm Capabilities
N/A HMAC-SHA-1 Expand
N/A HMAC-SHA2-224 Expand
N/A HMAC-SHA2-256 Expand
N/A HMAC-SHA2-384 Expand
N/A HMAC-SHA2-512 Expand

SHS 1780 Expand All First Validated: 5/25/2012

Operating Environment Algorithm Capabilities
N/A SHA-1 Expand
N/A SHA-224 Expand
N/A SHA-256 Expand
N/A SHA-384 Expand
N/A SHA-512 Expand

AES 2034 Expand All First Validated: 5/25/2012

Operating Environment Algorithm Capabilities
N/A AES-CBC Expand
N/A AES-ECB Expand

TDES 1311 Expand All First Validated: 5/25/2012

Operating Environment Algorithm Capabilities
N/A TDES-CBC Expand
N/A TDES-ECB Expand

Created October 05, 2016, Updated November 24, 2020