Computer Security Resource Center

Computer Security Resource Center

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    Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
7 Series and Zynq AES/MAC
Description
A Verilog implementation that has been synthesized into our 7 Series and Zynq products. This implementation has been governed in our internal revision control system. This implementation can be simulated via a synopsys VCS simulation/testbench framework.
Version
7 Series and Zynq
Type
HARDWARE
Vendor
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
USA
Contacts
Jason Moore
Jason.Moore@xilinx.com
505-798-4863

SHS 2034 Expand All First Validated: 3/29/2013

Operating Environment Algorithm Capabilities
N/A SHA-256 Expand

HMAC 1465 Expand All First Validated: 3/29/2013

Operating Environment Algorithm Capabilities
N/A HMAC-SHA2-256 Expand

AES 2363 Expand All First Validated: 3/29/2013

Operating Environment Algorithm Capabilities
N/A AES-CBC Expand

Created October 05, 2016, Updated November 24, 2020