Projects
Cryptographic Algorithm Validation Program
Cryptographic Algorithm Validation Program CAVP
Description
100Gbps FPGA core. AES-XTS 256 bit key, 128 bit multiple length text. Assocated GMAC, 256 bit key, 128 bit multiple length AAD, zero length PT.
Version
AES_1.0 (Firmware)
Vendor
Contacts
Soeren Laursen
slaursen@altera.com
+45 88701912
Morten Stribaek
mstribae@altera.com
+45 88701945
Operating Environment |
Algorithm Capabilities |
Mentor Questa Slm 10.2c
|
AES-ECB
Expand
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Created October 05, 2016, Updated November 24, 2020