Computer Security Resource Center

Computer Security Resource Center

This is an archive
(replace .gov by .rip)
    Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
BigIP i5820 TMM Implementation
Description
F5® BIG-IP® Application Delivery Controller and Firewall software running on F5 BIG-IP.
Version
13.1.0 (Firmware)
Type
SOFTWARE
Vendor
F5 Networks
401 Elliott Avenue West
Seattle, WA 98119
USA
Contacts
Maryrita Steinhour
m.steinhour@f5.com
206-272-7351
John Hughes
j.hughes@f5.com
206-272-6038

ECDSA 1230 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 ECDSA KeyGen (186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA KeyVer (186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA SigGen (186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 ECDSA SigVer (186-4) Expand

AES 4833 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 AES-CBC Expand
Intel(R) Xeon(R) CPU E5-1630 AES-GCM Expand
Intel(R) Xeon(R) CPU E5-1630 AES-GMAC Expand

Component 1466 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 KDF TLS Expand

Component 1465 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 KAS-ECC CDH-Component Expand

SHS 3975 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 SHA-1 Expand
Intel(R) Xeon(R) CPU E5-1630 SHA-256 Expand
Intel(R) Xeon(R) CPU E5-1630 SHA-384 Expand

RSA 2652 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 RSA SigGen (186-4) Expand
Intel(R) Xeon(R) CPU E5-1630 RSA SigVer (186-4) Expand

HMAC 3234 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA-1 Expand
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA2-256 Expand
Intel(R) Xeon(R) CPU E5-1630 HMAC-SHA2-384 Expand

DRBG 1692 Expand All First Validated: 11/3/2017

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) CPU E5-1630 Counter DRBG Expand

Created October 05, 2016, Updated November 24, 2020