Computer Security Resource Center

Computer Security Resource Center

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    Projects Cryptographic Algorithm Validation Program

Cryptographic Algorithm Validation Program CAVP

Implementation Name
vCMP TMM/Data Plane Implementation with NITROX III
Description
F5(R) BIG-IP(R) Application Delivery Controller and Firewall firmware running on F5 BIG-IP.
Version
14.1.0.3 EHF
Type
FIRMWARE
Vendor
F5 Networks
401 Elliott Avenue West
Seattle, WA 98119
USA
Contacts
Maryrita Steinhour
m.steinhour@f5.com
206-272-7351
Eric Raisters
e.raisters@f5.com
206-272-7580

C697 Expand All First Validated: 5/8/2019

Operating Environment Algorithm Capabilities
Intel(R) Xeon(R) E5 Expand
    		AES-CBC Expand
    Intel(R) Xeon(R) E5 Expand
      		AES-GCM Expand
      Intel(R) Xeon(R) E5 Expand
        		AES-GMAC Expand
        Intel(R) Xeon(R) E5 Expand
          		Counter DRBG Expand
          Intel(R) Xeon(R) E5 Expand
            		ECDSA KeyGen (186-4) Expand
            Intel(R) Xeon(R) E5 Expand
              		ECDSA KeyVer (186-4) Expand
              Intel(R) Xeon(R) E5 Expand
                		ECDSA SigGen (186-4) Expand
                Intel(R) Xeon(R) E5 Expand
                  		ECDSA SigVer (186-4) Expand
                  Intel(R) Xeon(R) E5 Expand
                    		HMAC-SHA-1 Expand
                    Intel(R) Xeon(R) E5 Expand
                      		HMAC-SHA2-256 Expand
                      Intel(R) Xeon(R) E5 Expand
                        		HMAC-SHA2-384 Expand
                        Intel(R) Xeon(R) E5 Expand
                          		KAS-ECC CDH-Component Expand
                          Intel(R) Xeon(R) E5 Expand
                            		KAS-ECC Component Expand
                            Intel(R) Xeon(R) E5 Expand
                              		KDF TLS Expand
                              Intel(R) Xeon(R) E5 Expand
                                		RSA SigGen (186-4) Expand
                                Intel(R) Xeon(R) E5 Expand
                                  		RSA SigVer (186-4) Expand
                                  Intel(R) Xeon(R) E5 Expand
                                    		SHA-1 Expand
                                    Intel(R) Xeon(R) E5 Expand
                                      		SHA-256 Expand
                                      Intel(R) Xeon(R) E5 Expand
                                        		SHA-384 Expand

                                        Created October 05, 2016, Updated November 24, 2020