Projects
Cryptographic Algorithm Validation Program
Cryptographic Algorithm Validation Program CAVP
Description
NITROX III chips implement SHA1/SHA2, 3DES/AES256 CBC, ModMul/ModEx/RSA, GCM and CTR modes, and SP800-90A DRBG. Perf: 5 to 30 Gbps encrypt/hash; 35K to 200K RSA 1024b ops/sec; 6K to 35K RSA 2048b ops/sec. NITROX III microcode also implements protocol-specific acceleration for IPSec and SSL.
Version
Nitrox III series die, v1.1 Nitrox III DRBG, r69306 (Firmware)
Vendor
Contacts
Mike Scruggs
mike.scruggs@cavium.com
(408) 943-7100
Fax: (408) 577-1992
TA (TAR) Ramanujam
tar@cavium.com
(408) 943-7383
Fax: (408) 577-1992
Operating Environment |
Algorithm Capabilities |
Cavium Nitrox III
|
Hash DRBG
Expand
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Created October 05, 2016, Updated November 24, 2020