This page contains information on some of the analysis from Round 2. It is not meant to be a comprehensive list.
AES-related Web Sites
Listed below are links to various public analysis efforts. Some may still contain information from Round 1.
- Block Cipher Lounge - Papers related to AES candidate algorithms. (Lars Knudsen, Vincent Rijmen)
- AES Round 2 Implementation Experience - Brian Gladman (UK)
- FPGA Implementation & Performance Evaluation of Serpent - Adam Elbirt, Christof Paar(WPI)
- Java Testing - Andreas Sterbenz (IAIK, Austria)
- cAESar Project - UCL Crypto Group in Belgium.
- Analysis from Louis Granboulan (ENS, France)
- Performance comparisons of the AES candidates from the submitters of Twofish
- AES Ciphers: Speed - Helger Lipmaa (Helsinki University of Technology, Finland)
NSA Hardware Analysis
NIST requested technical assistance from the National Security Agency (NSA) in performing a baseline hardware efficiency comparison of Round 2 finalists. Initial Plans for Estimating the Hardware Performance of AES Submissions describes the initial plans for that comparison.At the AES3 conference, Bryan Weeks of NSA gave a presentation of their preliminary report which was included in the AES3 Proceedings.
On May 15, 2000, NSA provided NIST with a final report on their evaluation: Hardware Performance Simluations of Round 2 Advanced Encryption Standard Algorithms.
Also available are the VHDL models developed by NSA to evaluate the hardware performance of the AES finalists: VHDL models [450KB]; README file.
Specific questions regarding the above information should be directed to Elaine Barker .