Physical Security Testing Workshop

Presentations
(in order of presentation)

Introduction to side channel attacks and non invasive attacks [PDF]
by Jan Blonk

Adequate physical security requirements [PDF]
by Jan Blonk

Typical Attack Techniques for Compromising Point of Sale PIN Entry Devices [PDF]
by Steven Bowles, Ben Cuthbert, and Wayne Stewart

Physical Security 101 [PDF]
by Tom Caddy

Potential Chemical Attacks on Coatings and Tamper Evident Seal Adhesives [PDF]
by Carol Cantlon,

SPA and DPA: Possible Testing Solutions and Associated Costs [PDF]
by Stan Kladko

Design and Validation Strategies for Obtaining Assurance in Countermeasures to Power Analysis and Related Attacks [PDF]
by Paul Kocher

A FIPS 140-2 evaluation could easily encompass physical security tests [PDF]
by Jean-Pierre Krimm

Composite Evaluations: Evaluations of Applications in High Security Multiple Application Modules [PDF]
by Raymond Makewell and Brian McKeon, PhD

Using Semiconductor Failure Analysis Tools for Security Analysis [PDF]
by Luther Martin

Studying LSI Tamper Resistance with Respect to Techniques Developed for Failure Analysis [PDF]
by Tsutomu Matsumoto, Shigeru Nakajima, Tadashi Shibata and Atsuhiro Yamagishi

TSRC and Side Channel Security Requirement [PDF]
by Tsutomu Matsumoto, Shinichi Kawamura, Kouichi Fujisaki, Naoya Torii, Shuichi Ishida, Yukiyasu Tsunoo, Minoru Saeki and Atsuhiro Yamagishi

Improving the DPA attack using Wavelet transform [PDF]
by Herve Pelletier and Xavier Charvet

FIPS 140-2 Physical Security Attack Scenarios [Removed]
by Mark Shin

Fault Induction and Environmental Failure Testing [PDF]
by Travis Spann

Experimental Results on INSTAC-8 Compliant Board [PDF]
by Yukiyasu Tsunoo, Toru Hisakado, Etsuko Tsujihara, Tsutomu Matsumoto, Shinichi Kawamura and Kouichi Fujisaki

Mind the Gap: Updating FIPS 140 [PDF]
by Steve Weingart

Side-Channel Attacks: Ten Years After Its Publication and the Impacts on Cryptographic Module Security Testing [PDF]
by YongBin Zhou and DengGuo Feng

Introduction and Welcome Message from "IPA" and "INSTAC" [PDF]

by Tsutomu Matsumoto

The Increasing Complexity & Need for Validation [PDF]

by Paul Kocher

Physical Security 101 [Powerpoint]
by Tom Caddy

Experimental Results of Attacks Against Ciphers Implemented on INSTAC-8 Compliant Board [PDF]
by Yukiyasu Tsunoo, Toru Hisakado, Etsuko Tsujihara, Tsutomu Matsumoto, Shinichi Kawamura and Kouichi Fujisaki

Design & Validation Strategies for Obtaining Assurance in Countermeasures to Power Analysis & Related Attacks [PDF]
by Paul Kocher

SPA and DPA - Possible Testing Solutions and Associated Costs [Powerpoint]
by Stan Kladko

Physical Security Protections [Powerpoint]
by Mark Shin

Mind the Gap: Updating FIPS 140 [Powerpoint]
by Steve Weingart

Studying LSI Tamper Resistance with Respect to Techniques Developed for Failure Analysis [PDF]
by Tsutomu Matsumoto, Shigeru Nakajima, Tadashi Shibata and Atsuhiro Yamagishi

Potential Chemical Attacks on Coatings and Tamper Evident Seal Adhesives [Powerpoint]
by Carol Cantlon

Fault Induction & Environmental Failure Testing (EFT) [Powerpoint]
by Travis Spann

Typical Attack Techniques for Compromising Point of Sale PIN Entry Devices [Powerpoint]
by Steven Bowles

Software Hardening & FIPS 140 [Powerpoint]
by Eugen Bacic and Gary Maxwell

FIPS 140 Validation for a “System-on-a-Chip” [Powerpoint]
by Chris Brych

Cryptographic Module Validation Program - Where security starts … [Powerpoint]
by Randall J. Easter

TSRC and Side Channel Security Requirement [Powerpoint]
by Shinichi Kawamura

FIPS 140-3 - Status and Schedules [Powerpoint]
by Allen Roginksy

FIPS 140-3 Section 5 – Physical Security [Powerpoint]
by Randall J. Easter